0:00:14first of a thank you for your coming uh
0:00:17just like is done in in this the bug done suit fronts look you know
0:00:21and with that of my supervisor sleep could see
0:00:24a a C shot mind think my oh
0:00:27and this presentation i
0:00:29uh are present that you were technique
0:00:32a a for mapping that i now
0:00:35in memory based architecture
0:00:37and application we have been utilising to uh but in iraq i interleaver architecture which is normally used in
0:00:43i a coding
0:00:44a you your where you have a four parts first we present up our problem and then we model our
0:00:50and next we prepare but a good on that how
0:00:52uh we saw can free memory mapping
0:00:55and it last we conclude our presentation uh
0:00:57uh with the feature perspective
0:01:00so first just problem formulation and uh first we describe a application and which we apply yeah about the
0:01:05a a a good time it's that that codes
0:01:08and which is i perform us uh uh of our uh uh but correction codes uh uh with the forty
0:01:12characteristics first of all that but uh
0:01:15but from is uh very close to the capacity of channels and second in
0:01:19and the use i did you decoding to approximate date
0:01:23so what is the problem with that date of decoding that we have to uh process data are more than
0:01:27one time so
0:01:29but i that eight applications it is very slow and it to improve the
0:01:33uh to put
0:01:34we need a better or or decoder architecture in which we have more than and processing elements and
0:01:39it the do we have a number of memory bank
0:01:41and then we haven't interconnection connection at five big be in processing elements and memory banks to connect processes that
0:01:47is architecture is good if uh uh uh at each time instance all a processing demons
0:01:53i with access different memory banks
0:01:55but what happens if uh more than and processing much faster access
0:02:00and the same memory bank
0:02:02at the same time instance
0:02:04in that case
0:02:06can problem course and due to this can problem uh a but tense east
0:02:12and uh uh
0:02:13assume that you we need a first so we also and use a hardware cost
0:02:17and a to put has been used
0:02:19so in this uh are talk will we present a technique to remove these uh and fit problem
0:02:24for memory based architecture
0:02:27so first we a from your our problem to they but we have a a you that tally men send
0:02:31people people single email
0:02:33and similarly that you we have a point um but all for a main memory banks
0:02:39and simply lady where you have a T time instances in which uh process it's font process is that you
0:02:44men's first in natural order and then interleaved order
0:02:47which is the requirement for that of would be a
0:02:50so what is a uh a problem the problems can simple we want to store that men in memory in
0:02:56such a manner that that each time instant
0:02:58a all the process as X is uh data in the memory banks without any can
0:03:04so i that's a model example that we have been prepared
0:03:06and use in these uh oh
0:03:09and we have at work that alley men seem that you reality processing meant
0:03:13and uh also we have a a a time instance is for for natural or out and for for to
0:03:18go to
0:03:19in which we processed assessed our data
0:03:22so first we give you what is that additional approach
0:03:24to solve this problem that they use an up what used to but a can fit excess get off in
0:03:28which all the that elements at be presented by a or
0:03:32and then we can the no was which we need to excess in better for example at you when we
0:03:36need to excess uh as zero forty it's so
0:03:39and we can and these nodes to the edges
0:03:42so idiot a two we need one five and nine so we can have these uh north so the use
0:03:46and seem we continue and we prepare a what to comfort excess get off
0:03:51so after the application of what off we yeah
0:03:54use an node the colouring problem
0:03:57in the nodes which have been connected to the same image has been giving the different colour
0:04:01but uh but is a problem the problem that the note culling is then P complete so we do not
0:04:06of any L go time to find minimum note can
0:04:09and if we have some of uh you stick this of goals are stick can not find a minimum note
0:04:13coding so we can find a a minimum
0:04:15memory banks say we need to uh to be memory men's
0:04:19but uh if we use note coding approach it is not always possible to find a a a a a
0:04:24a team memory meant
0:04:25at the problem that the not coding it the able to find a architecture do and in memory mapping for
0:04:30example we have a some uh a specific interconnection network and we want to map power data
0:04:35using the these interconnection networks so
0:04:38he's the sticks on able to find these type of approach
0:04:42so we and attack of this proposal by put of um by introducing a transportation problem modeling of or
0:04:51and uh using this technique we can uh find out a architecture granted memory mapping if interleavers law allowed to
0:04:57find that
0:04:59so yeah memory can first one is it to to the conflict the of is quite normal that that to
0:05:04each time instance all the memory men that memory ben sorry presented with the colours too
0:05:08all the memory ben should be different
0:05:10and uh a second one is uh
0:05:13that the
0:05:14these that that should be map been one and only one memory bank here the board in natural into the
0:05:18order you should be all in the same memory men
0:05:21yeah is there so it all is
0:05:22all they always in that at memory bank
0:05:25at in the with order metrics
0:05:27so now we talk about one morning
0:05:29so how we prepare a but by part go off a we paper our by but at a graph on
0:05:33which on one are as we have all the time instance on of size we have all that that north
0:05:37and we can that time instances is with that that no was at we need to
0:05:41at which we need to process this that elements for example at T one
0:05:44we need you of for that so we can at these you for that with a time instance a
0:05:49or time not be one
0:05:50in that that we can't any and we we connect all that that don't nodes we a about
0:05:54uh time instances for natural order
0:05:57similarly that you we continue and we can at the to one and eleven
0:06:00uh uh the uh
0:06:02uh uh that i time instance T five
0:06:05and uh
0:06:07a the
0:06:07i i in that that we construct a but
0:06:10the will bite but i'd go off
0:06:11so the are some definitions and false for definition is that the with the semi two factor is
0:06:16is a
0:06:17to regular off at to why but this is there of i is equal to the number of time but
0:06:20this is
0:06:22and uh at each you know what we have been is uh in a uh is it exactly two edges
0:06:26here you can see that
0:06:28all the nodes uh are in to do with two which is which is been to that the board lines
0:06:31here and here
0:06:33and all that time nodes have been included in this
0:06:36and sub off
0:06:38so this is are
0:06:40to what on model only there at the if we have a
0:06:43and D two K or two Q plus fun at each time instant
0:06:46then we have a K number of this and semi two factors here you can see it and for example
0:06:51these in this example
0:06:54we have a digity to so which means that we have of one
0:06:57and a semi two factor
0:06:59so using this sort go terms and uh this do the proofs are to in the paper so you can
0:07:03find these proves in in the paper
0:07:06so not we can about about the will by part at their off uh into the task problem or in
0:07:11so we can find a conflict free memory mapping
0:07:14that's prediction problem is quite simple uh we have a a just like a bite but at that off you
0:07:18only a one once we have produce a
0:07:20and side we have a consumers
0:07:22and it seems that it is that a presentation of metrics on on each it was we have a
0:07:27uh port use an each on we have a a consumers
0:07:30so the are some other variables first one is the capacity of to produce and consume but yeah it you
0:07:35we can put the cap to in front of the
0:07:37and port you site and are we
0:07:39a put the
0:07:40and kept gap is T of the consumer in front of it
0:07:43so also we have a two
0:07:45um between the
0:08:00so we have a would between uh
0:08:02and pose uh can produce or and consumers uh
0:08:06and also we have a a a at forty each would we have a cup T of that would and
0:08:10also cost to put a support each men
0:08:12of this root for example at you can see that uh
0:08:15poured use a one is a can i have a would between and consumer but M one and you do
0:08:19and also we have us some but a variables X X one which is a
0:08:23a press of that would do all one one you which is a a cost to a support when D
0:08:27meant on this rule
0:08:28in that if we prepare a or the task quotation matt takes and put all the values a
0:08:32now we can what a but that there will by but i to get off on these transportation metric
0:08:37we put the values Z R zero is uh all that that don't know that an all the
0:08:42time note that consumers
0:08:43so we have for the zero is connected with T one and T six a week in give the values
0:08:49in the cell which is in front of T one zero and a T six zero
0:08:53but now we have some of the optimisation for a hard the the for of a conflict free memory mapping
0:08:58or hardware architecture first one it's
0:09:00at each time instance we can uh X has only one that that so we get better
0:09:04keep track of S T able to one
0:09:06because a we have a a a a a that you meant that each time instant
0:09:11similarly is since we are not concede in the cost of interconnection networks so we can keep the the cost
0:09:16value you one
0:09:17and for all that too
0:09:19image is we continue that that uh put putting said when we you have a connection to T two T
0:09:23five so we put that values
0:09:25in front of these uh uh consumers
0:09:28in that the we continue and compute of their off
0:09:31also also the are that a variable which is important uh uh is a name of the process sort of
0:09:36each excess that that that must at that time instant
0:09:39uh a a but before the uh
0:09:41and since we are finding a semi two factors so all the
0:09:44and yeah
0:09:46supply of all the producers and uh the amount of all the "'cause" you must have been giving a value
0:09:50too because uh we are can see be baiting a semi two factor
0:09:55now uh for uh architecture ended mapping we put a name of the process as also
0:10:01because we need just process of for example they are the do you need to a process that process of
0:10:05P once so we give the value P one
0:10:07in front uh in the a do we just got to be D one and zero
0:10:11that that if we put all the processes and we
0:10:14all these metrics model of mapping problem it's all the
0:10:17and cost and uh get best of the was a T we move these man and only the process name
0:10:22would be knee in in this
0:10:25so now we continue and would well
0:10:27a well go time got them is quite simple first we find a cycle
0:10:30if the cycle is completed at at steps we check but that just completed or not
0:10:34we find a semi two factor and then remove the semi two factor and are
0:10:41and then we find as case case semi two factors if it if the just find then yes
0:10:46that what them is completed if not then we can at each step we can go back out i at
0:10:50of computer of a algorithm
0:10:52so is to a some don't to target the at track is but if there so we give a gift
0:10:56first group um emily bank be note
0:10:59and uh
0:11:00after the giving the memory bank we can reduce the capacity of both producers and consumers here the since one
0:11:07and then be bank is at a good to to the capacity of the mm a board the put a
0:11:11second the consumer have been reduced by one
0:11:14no we continue and we give a second
0:11:16mm memory band to the process of just next because we are constructing a a better of the looks so
0:11:21the next was that so
0:11:22P to so we give "'em" emily been be one to this process a
0:11:26so now the the uh get T of the um
0:11:30um put a consumers one has been complete so we can remove all the is uh
0:11:35uh produce of which have been a connected with this uh consumer
0:11:38so it have been a move from these from the current semi two factor
0:11:42simulated to sec in to don't had been assigned a similar to the mm memory bank
0:11:47which connected with for you know order to follow the second constraint that uh each data limit should be mapping
0:11:53in and only one memory bank
0:11:55now the capacity of the body of uh for is also completed
0:11:58in that we now we have to again have to follow the but that a rule
0:12:04the so be one have been a look at did uh a a uh one have been a look at
0:12:07you to um emily bank to one so now for the next to
0:12:11and but it's you've dark a mapping
0:12:14the next process uh a uh the probably process of which is before the P even has been a good
0:12:18deed a memory bank be not
0:12:21uh but this cycle is not complete just T uh here you can see that the process of which is
0:12:25before the P even has a
0:12:27we just P T
0:12:28so we gonna sign up P to D a memory bank be not
0:12:32in that they seem the yeah
0:12:34now the a a D model of uh
0:12:37boating sir seven is complete so we can remove the that produces that have been connected with this
0:12:41and uh consumer
0:12:43and in that if we have been continue had you can say that P two is no can net uh
0:12:47a signed with be know so the next process so
0:12:50B to you have been assigned a memory bank B even
0:12:53and uh again the up is um the monte is from phil so we can remove the other
0:12:58put the saying that if we continue and the we apply a well go time
0:13:03and until the cycle is completed D you can see that the and cycle is completed because uh these no
0:13:09buddy set a consumer with the value of one
0:13:12in a have the
0:13:14but with that you can see that there's likely is not computed because uh some producers
0:13:18a you on is left but we fulfilled
0:13:21so we can uh uh a uh guy you go back and
0:13:25is uh construct on that the cycle
0:13:27a a you can and for constructing another the cycle we used a a a a a a yeah
0:13:32produce says of have been already and deleted it for example are you can see there seven to you did
0:13:37and is connected T four
0:13:39so using this seven we can now a look at a a memory bank to well but
0:13:45from the at you can see that the
0:13:47a a seven
0:13:49B one in the are um or do T six
0:13:54oh next to the P one with this P to has a memory bank of location be note
0:13:58which means that the P to D which is next to P node in the old use seven must be
0:14:03the same in banks so here
0:14:05this uh P to you must be a same memory bank which is be what
0:14:10and now we can uh you'd use the one car get best steel both producers and
0:14:14"'cause" you might by one in that to we continue and we
0:14:17yeah construct our second cycle
0:14:20after that can section you can see that
0:14:22the uh model for although um consumers have been fulfilled so which means there this i a vector that being
0:14:28complete it so we can remove this semi two factor and uh
0:14:32and now you can see that only one route disconnected with all the producers and consumers which means that we
0:14:37need only third memory band
0:14:38to look with to all the two
0:14:41in that way we have been a well go to is completed
0:14:44and uh now we find this memory mapping
0:14:48now we can transform a and here you can the six says a
0:14:52memory bank B B one so we can put six in the be even
0:14:56say at is the representation so you can see the relative to architecture
0:15:00you can see that the gain is a is after uh a that's so in at every time instance
0:15:07and use is all these uh after the data memory event
0:15:12so the so so now for the conclusion we we solve a computationally hard mean mapping problem and uh
0:15:19also also we propose a transportation problem modeling to file architecture don't and memory mapping
0:15:24and for pitch of perspective we keep the cost to a at each ut once so now we want to
0:15:29lose the complexity of a dictation but we want to give some value you to these rules
0:15:33so that's uh we can do the complexity and also we want to extend this a some to other interconnection
0:15:39and such as that the uh you re
0:15:43a since we have a king on high level sent is is we want we are currently to developing a
0:15:46to uh which such as is the construction of memory based architecture is and we generate to
0:15:52and a conflict free memory mapping and also and technician architecture
0:15:56and thanks for your question
0:15:59thank you for attention
0:16:07pretty quest