first of a thank you for your coming uh just like is done in in this the bug done suit fronts look you know and with that of my supervisor sleep could see a a C shot mind think my oh and this presentation i uh are present that you were technique a a for mapping that i now in memory based architecture and application we have been utilising to uh but in iraq i interleaver architecture which is normally used in i a coding a you your where you have a four parts first we present up our problem and then we model our problem and next we prepare but a good on that how uh we saw can free memory mapping and it last we conclude our presentation uh uh with the feature perspective so first just problem formulation and uh first we describe a application and which we apply yeah about the a a a good time it's that that codes and which is i perform us uh uh of our uh uh but correction codes uh uh with the forty characteristics first of all that but uh but from is uh very close to the capacity of channels and second in and the use i did you decoding to approximate date so what is the problem with that date of decoding that we have to uh process data are more than one time so but i that eight applications it is very slow and it to improve the uh to put we need a better or or decoder architecture in which we have more than and processing elements and it the do we have a number of memory bank and then we haven't interconnection connection at five big be in processing elements and memory banks to connect processes that memory is architecture is good if uh uh uh at each time instance all a processing demons i with access different memory banks but what happens if uh more than and processing much faster access and the same memory bank at the same time instance in that case um can problem course and due to this can problem uh a but tense east and uh uh assume that you we need a first so we also and use a hardware cost and a to put has been used so in this uh are talk will we present a technique to remove these uh and fit problem for memory based architecture so first we a from your our problem to they but we have a a you that tally men send people people single email and similarly that you we have a point um but all for a main memory banks yeah and simply lady where you have a T time instances in which uh process it's font process is that you men's first in natural order and then interleaved order which is the requirement for that of would be a so what is a uh a problem the problems can simple we want to store that men in memory in such a manner that that each time instant a all the process as X is uh data in the memory banks without any can so i that's a model example that we have been prepared and use in these uh oh and we have at work that alley men seem that you reality processing meant and uh also we have a a a time instance is for for natural or out and for for to go to in which we processed assessed our data so first we give you what is that additional approach to solve this problem that they use an up what used to but a can fit excess get off in which all the that elements at be presented by a or and then we can the no was which we need to excess in better for example at you when we need to excess uh as zero forty it's so and we can and these nodes to the edges so idiot a two we need one five and nine so we can have these uh north so the use and seem we continue and we prepare a what to comfort excess get off so after the application of what off we yeah use an node the colouring problem in the nodes which have been connected to the same image has been giving the different colour but uh but is a problem the problem that the note culling is then P complete so we do not of any L go time to find minimum note can and if we have some of uh you stick this of goals are stick can not find a minimum note coding so we can find a a minimum memory banks say we need to uh to be memory men's but uh if we use note coding approach it is not always possible to find a a a a a a team memory meant at the problem that the not coding it the able to find a architecture do and in memory mapping for example we have a some uh a specific interconnection network and we want to map power data using the these interconnection networks so he's the sticks on able to find these type of approach so we and attack of this proposal by put of um by introducing a transportation problem modeling of or problem and uh using this technique we can uh find out a architecture granted memory mapping if interleavers law allowed to find that so yeah memory can first one is it to to the conflict the of is quite normal that that to each time instance all the memory men that memory ben sorry presented with the colours too all the memory ben should be different and uh a second one is uh that the these that that should be map been one and only one memory bank here the board in natural into the order you should be all in the same memory men yeah is there so it all is all they always in that at memory bank at in the with order metrics so now we talk about one morning so how we prepare a but by part go off a we paper our by but at a graph on which on one are as we have all the time instance on of size we have all that that north and we can that time instances is with that that no was at we need to at which we need to process this that elements for example at T one we need you of for that so we can at these you for that with a time instance a or time not be one in that that we can't any and we we connect all that that don't nodes we a about uh time instances for natural order similarly that you we continue and we can at the to one and eleven uh uh the uh uh uh that i time instance T five and uh a the i i in that that we construct a but the will bite but i'd go off so the are some definitions and false for definition is that the with the semi two factor is is a to regular off at to why but this is there of i is equal to the number of time but this is and uh at each you know what we have been is uh in a uh is it exactly two edges here you can see that all the nodes uh are in to do with two which is which is been to that the board lines here and here and all that time nodes have been included in this and sub off so this is are to what on model only there at the if we have a and D two K or two Q plus fun at each time instant then we have a K number of this and semi two factors here you can see it and for example these in this example uh we have a digity to so which means that we have of one and a semi two factor so using this sort go terms and uh this do the proofs are to in the paper so you can find these proves in in the paper so not we can about about the will by part at their off uh into the task problem or in so we can find a conflict free memory mapping that's prediction problem is quite simple uh we have a a just like a bite but at that off you only a one once we have produce a and side we have a consumers and it seems that it is that a presentation of metrics on on each it was we have a uh port use an each on we have a a consumers so the are some other variables first one is the capacity of to produce and consume but yeah it you we can put the cap to in front of the and port you site and are we a put the and kept gap is T of the consumer in front of it so also we have a two um between the so we have a would between uh and pose uh can produce or and consumers uh and also we have a a a at forty each would we have a cup T of that would and also cost to put a support each men of this root for example at you can see that uh poured use a one is a can i have a would between and consumer but M one and you do and also we have us some but a variables X X one which is a a press of that would do all one one you which is a a cost to a support when D meant on this rule in that if we prepare a or the task quotation matt takes and put all the values a now we can what a but that there will by but i to get off on these transportation metric we put the values Z R zero is uh all that that don't know that an all the time note that consumers so we have for the zero is connected with T one and T six a week in give the values uh in the cell which is in front of T one zero and a T six zero but now we have some of the optimisation for a hard the the for of a conflict free memory mapping or hardware architecture first one it's at each time instance we can uh X has only one that that so we get better keep track of S T able to one because a we have a a a a a that you meant that each time instant similarly is since we are not concede in the cost of interconnection networks so we can keep the the cost value you one and for all that too image is we continue that that uh put putting said when we you have a connection to T two T five so we put that values in front of these uh uh consumers in that the we continue and compute of their off also also the are that a variable which is important uh uh is a name of the process sort of each excess that that that must at that time instant uh a a but before the uh and since we are finding a semi two factors so all the and yeah supply of all the producers and uh the amount of all the "'cause" you must have been giving a value too because uh we are can see be baiting a semi two factor now uh for uh architecture ended mapping we put a name of the process as also because we need just process of for example they are the do you need to a process that process of P once so we give the value P one in front uh in the a do we just got to be D one and zero that that if we put all the processes and we all these metrics model of mapping problem it's all the and cost and uh get best of the was a T we move these man and only the process name would be knee in in this medics so now we continue and would well a well go time got them is quite simple first we find a cycle if the cycle is completed at at steps we check but that just completed or not we find a semi two factor and then remove the semi two factor and are uh and then we find as case case semi two factors if it if the just find then yes that what them is completed if not then we can at each step we can go back out i at of computer of a algorithm so is to a some don't to target the at track is but if there so we give a gift first group um emily bank be note and uh after the giving the memory bank we can reduce the capacity of both producers and consumers here the since one and then be bank is at a good to to the capacity of the mm a board the put a second the consumer have been reduced by one no we continue and we give a second mm memory band to the process of just next because we are constructing a a better of the looks so the next was that so P to so we give "'em" emily been be one to this process a so now the the uh get T of the um um put a consumers one has been complete so we can remove all the is uh uh produce of which have been a connected with this uh consumer so it have been a move from these from the current semi two factor simulated to sec in to don't had been assigned a similar to the mm memory bank which connected with for you know order to follow the second constraint that uh each data limit should be mapping in and only one memory bank now the capacity of the body of uh for is also completed in that we now we have to again have to follow the but that a rule the so be one have been a look at did uh a a uh one have been a look at you to um emily bank to one so now for the next to and but it's you've dark a mapping the next process uh a uh the probably process of which is before the P even has been a good deed a memory bank be not uh but this cycle is not complete just T uh here you can see that the process of which is before the P even has a we just P T so we gonna sign up P to D a memory bank be not in that they seem the yeah now the a a D model of uh boating sir seven is complete so we can remove the that produces that have been connected with this and uh consumer and in that if we have been continue had you can say that P two is no can net uh a signed with be know so the next process so B to you have been assigned a memory bank B even and uh again the up is um the monte is from phil so we can remove the other put the saying that if we continue and the we apply a well go time and until the cycle is completed D you can see that the and cycle is completed because uh these no buddy set a consumer with the value of one in a have the matter but with that you can see that there's likely is not computed because uh some producers a you on is left but we fulfilled so we can uh uh a uh guy you go back and is uh construct on that the cycle a a you can and for constructing another the cycle we used a a a a a a yeah produce says of have been already and deleted it for example are you can see there seven to you did and is connected T four so using this seven we can now a look at a a memory bank to well but process from the at you can see that the a a seven B one in the are um or do T six yeah oh next to the P one with this P to has a memory bank of location be note which means that the P to D which is next to P node in the old use seven must be the same in banks so here this uh P to you must be a same memory bank which is be what and now we can uh you'd use the one car get best steel both producers and "'cause" you might by one in that to we continue and we yeah construct our second cycle after that can section you can see that the uh model for although um consumers have been fulfilled so which means there this i a vector that being complete it so we can remove this semi two factor and uh and now you can see that only one route disconnected with all the producers and consumers which means that we need only third memory band to look with to all the two in that way we have been a well go to is completed and uh now we find this memory mapping now we can transform a and here you can the six says a memory bank B B one so we can put six in the be even say at is the representation so you can see the relative to architecture you can see that the gain is a is after uh a that's so in at every time instance and use is all these uh after the data memory event so the so so now for the conclusion we we solve a computationally hard mean mapping problem and uh also also we propose a transportation problem modeling to file architecture don't and memory mapping and for pitch of perspective we keep the cost to a at each ut once so now we want to lose the complexity of a dictation but we want to give some value you to these rules so that's uh we can do the complexity and also we want to extend this a some to other interconnection networks and such as that the uh you re a since we have a king on high level sent is is we want we are currently to developing a to uh which such as is the construction of memory based architecture is and we generate to and a conflict free memory mapping and also and technician architecture and thanks for your question thank you for attention pretty quest okay