DATA-PATH AND MEMORY ERROR COMPENSATION TECHNIQUE FOR LOW POWER JPEG IMPLEMENTATION
DSP Algorithm and Architecture Optimization for Hardware Implementation
Presented by: Chaitali Chakrabarti, Author(s): Yunus Emre, Chaitali Chakrabarti, Arizona State University, United States
The paper presents a novel technique to mitigate effects of data-path and memory errors in JPEG implementations. These errors are mainly caused by voltage scaling and process variation in scaled technologies. We characterize the data-path and memory errors and derive a probability distribution of the total number of errors. We propose an algorithm-specific technique that corrects most errors after the quantization step in JPEG encoder by exploiting the characteristics of the quantized coefficients. Simulation results show that the proposed technique has a PSNR performance degradation of around 1.5 dB compared to the error-free case and 4 dB improvement compared to the no correction case at 0.75 bpp when BER=10^(-4). This is achieved with small circuitry overhead and no memory overhead.