MULTI-RATE POLYPHASE DSP AND LMS CALIBRATION SCHEMES FOR OVERSAMPLED DATA CONVERSION SYSTEMS
DSP Algorithm and Architecture Optimization for Hardware Implementation
Přednášející: Subhanshu Gupta, Autoři: Subhanshu Gupta, University of Washington, United States; Yi Tang, Qualcomm Inc., Singapore; Kuang-Wei Cheng, Institute of Microelectronics, Singapore; Jeyanandh Paramesh, Carnegie Mellon University, United States; David Allstot, University of Washington, United States
Schemes for calibrating oversampled A/D systems are presented. Conventional full-rate LMS calibration has two limitations: slow convergence and high complexity/power dissipation for high adaptive filter orders and sampling frequencies. Half- (fs/2) and quarter-rate (fs/4) LMS calibration are used to reduce the complexity. Noble identities and polyphase decimation are used to match digital noise-cancellation filters to the transfer functions of an analog fourth-order cascade sigma-delta A/D. Energy savings up to 30% compared to conventional full-rate (fs) schemes are confirmed using an Altera Stratix II field-programmable gate array. Using OSR = 8, the A/D achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.
Informace o přednášce
| Nahráno: | 2011-05-26 14:25 - 14:45, Club H |
|---|---|
| Přidáno: | 9. 6. 2011 23:30 |
| Počet zhlédnutí: | 78 |
| Rozlišení videa: | 1024x576 px, 512x288 px |
| Délka videa: | 0:21:43 |
| Audio stopa: | MP3 [7.43 MB], 0:21:43 |
Příbuzné přednášky
0:16:30
DATA-PATH AND MEMORY ERROR COMPENSATION TECHNIQUE FOR LOW POWER JPEG IMPLEMENTATION
DSP Algorithm and Architecture Optimization for Hardware Implementation
Přidáno: 9. 6. 2011 23:29
0:24:48
IMPROVING KERNEL-ENERGY TRADE-OFFS FOR MACHINE LEARNING IN IMPLANTABLE AND WEARABLE BIOMEDICAL APPLICATIONS
DSP Algorithm and Architecture Optimization for Hardware Implementation
Přidáno: 9. 6. 2011 23:09
Komentáře